Within the semiconductor industry, it is often desirable to be able to examine an existing integrated circuit (IC) to obtain design and/or layout information therefrom. By way of example, the process of designing and then successfully fabricating a large-scale semiconductor circuit frequently involves numerous iterations in which the design and/or layout of the circuit is successively modified to correct for errors in circuit design, functionality, layout connectivity, etc. In other instances, it is desirable to reverse engineer an existing IC to extract schematic or other netlist information. Both of these processes normally involve arduous, time consuming manual labor.
By way of example, the reverse engineering process typically begins by having an engineer, or one skilled in the art, visually inspect the wafer using a microscope to identify certain structures. This involves painstakingly identifying each of the various cells, logic gates (e.g., NAND, NOR, etc.) and other elements employed within the integrated circuit. Next, the engineer manually attempts to reconstruct a more complete circuit schematic by visually tracing the metal interconnections between each of the circuit elements. It is not uncommon for this type of reverse engineering task to take six months or more to complete. Thus, manual design verification and connectivity checking is one of the principle reasons why the design cycle for large scale or for very large scale integrated circuits is so exceedingly long.
Therefore, what is needed is an automated method for inspecting an integrated circuit die or wafer for the purpose of extracting design and/or layout information therefrom. As will be seen, the present invention provides an automated system for generating a netlist and other circuit information from the topological image of a fabricated chip. To achieve this, the present invention utilizes an integrated system which combines both hardware and software elements. Thus, the invented system is capable of radically reducing the cycle time for the design and fabrication of an IC, or for the reverse engineering of an existing IC. In some cases, a circuit that would normally take several months to examine and reverse engineer by hand, can be completely analyzed by the present invention in a matter of hours.